06/11/2024
By Mushaheeda
376
Blog

Physical Design Engineer at Samsung | Bangalore • India

Physical Design Engineer at Samsung, Samsung Electronics is a global chief in its era, renowned for its innovation and management in a wide range of industries, from client electronics to semiconductors. Established in 1969, Samsung has emerged as one of the world’s maximum diagnosed manufacturers, always pushing the boundaries of an era in sectors such as smartphones, TVs, wearables, and the Internet of Things (IoT). With its superior semiconductor solutions, Samsung is at the forefront of growing the destiny of reminiscence, device LSI, foundry, and LED technology.

Role: Physical Design Engineer

Company: Samsung R&D Institute India

Company: Bangalore • India

Work Type: Full–time

Physical Design Engineer at Samsung

As a Physical Design Engineer at Samsung Semiconductor, you can work on cutting-edge technology in the development of subsequent technology SOCs, together with cell processors and connectivity chips. Your function will incorporate complicated responsibilities like synthesis, vicinity and direction, static timing analysis (STA), and making sure that designs meet the favored performance, strength, and place (PPA) requirements. You will use advanced devices like ICC, DC, VSLP, and Redhawk for SOC layout and optimization.

About Company

Samsung Semiconductor is searching for a pretty expert Physical Design Engineer to artwork on the next-era System on Chips (SOCs) in the regions of mobile utility processors, modem sub-structures, and connectivity chips. The role includes complex SOC pinnacle bodily implementation duties inclusive of synthesis, vicinity and course, static timing assessment (STA), timing closure, and bodily sign-offs. As part of the crew, you’ll artwork with the cutting-edge era, control layout demanding situations, and make sure of maximum wonderful overall performance, power, and area (PPA) exchange-offs. .

Role and Responsibilities

SOC Top Physical Implementation: Lead the bodily design responsibilities for subsequent-gen SOCs, collectively with synthesis, area and direction, STA, timing closure, and bodily signal-offs.

Timing and Power Optimization: Work on optimizing electricity, common performance, and place (PPA) for complicated designs, ensuring first-rate consequences at some stage in various tasks.

Floor Planning and Design: Participate in top-level floor planning, partition shaping, pin placement, and clock and sign-making plans.

SOC Design Flow: Use enterprise-fashionable gear (e.g., ICC/DC/PT/VSLP/Redhawk/Calibre) for synthesis, physical design, and timing closure, and recognize their competencies.

Timing Closure and Sign-offs: Ensure complete-chip timing closure, strength checking, right judgment equivalence checking, and physical format verification (LVS/DRC).

Advanced Process Node Design: Familiar with superior method nodes (e.g., 8nm/5nm) and their associated issues which encompass manufacturability, power, and signal integrity.

Design Issues and Debugging: Resolve regular SOC problems together with a couple of voltage/clock domains, ESD strategies, and bundle deal interactions. Debug LVS/DRC problems at the block and chip degree.

Required Skills and Qualifications

Education: B.E./B.Tech, M.E./M.Tech, or Ph.D. In Electrical Engineering, Computer Engineering, or associated fields.

Experience: Hands-on enjoy with huge SOC designs, timing closure, electricity optimization, and bodily design verification.

Technical Skills: Expertise in company-popular equipment (ICC, DC, PT, VSLP, Redhawk, Calibre), scripting languages (Perl, Tcl), and SOC layout flows.

Familiarity: Deep sub-micron designs (e.g., 8nm/5nm), and understanding of complicated SOC troubles collectively with combined signal integration, voltage domains, and clock area crossing.

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