ASIC Engineer, Design | Bengaluru
Meta’s Infrastructure agency plays a pivotal characteristic in making this imaginative and prescient truth by designing superior hardware answers. Among the important thing factors of this hardware is the development of Application-Specific Integrated Circuits (ASICs), which allow the excessive-average basic performance, and power-inexperienced processing required for facts center packages. To guide this, Meta is trying to find talented ASIC Design Engineers with experience in growing global-splendor SoCs (Systems on Chips) and IP (Intellectual Property).
Role: ASIC Engineer, Design
Company: Meta
Experience: 3 – 6 years
Salary: Not Disclosed
Location: Bengaluru
About Company
Meta is hiring ASIC Design Engineers to join its Infrastructure employer. These engineers will awareness on developing complicated SoC and IP for facts middle applications. Responsibilities encompass micro-shape improvement, RTL coding with Verilog/System Verilog, and participating with verification and implementation teams. Candidates have to have a Bachelor’s diploma in a technical location and 3+ years of experience in silicon development, RTL, or SoC format. Preferred qualifications encompass reveling in facts path improvement and timing closure. At Meta, you’ll be a part of a modern crew shaping the destiny of connectivity via modern-day technology.
Job Description
As an ASIC Engineer, Design, you may be a vital part of Meta’s hardware development organization. You will make contributions to the micro-shape improvement and RTL (Register Transfer Level) layout of complex records center packages. Your artwork will span more than one elements of silicon format, which encompass electricity optimization, timing closure, and verification, to deliver state-of-the-art, scalable solutions that can be crucial to Meta’s infrastructure.
Key Responsibilities
Micro-Architecture Development
You can be chargeable for designing the micro-shape for critical components inside Meta’s custom silicon. This consists of defining the shape of manipulate and information course IPs, which shape the muse of Meta’s hardware for high-performance computing.
RTL Development
Using Verilog, System Verilog, and High-Level Synthesis (HLS), you will translate the micro-shape into RTL code. Your designs can be optimized for power universal performance, normal overall performance, and scalability, ensuring they’re able to meet the rigorous desires of facts center applications.
Design Verification and Emulation Collaboration
You will work carefully with verification and emulation agencies to amplify test plans and make sure that the designs characteristic as meant. This includes debugging and refining the layout based totally on remarks from simulation and emulation techniques.
Synthesis and Power Optimization
Collaborating with the implementation organization, you could make certain that designs are optimized for energy consumption, synthesis, and timing closure. This consists of figuring out regions for improvement in terms of power’s usual overall performance and performance, a crucial consideration in records middle environments in which strength consumption is a massive factor.
Soft and Hard IP Selection
You are probably involved in the identification, desire, and integration of every smooth and tough IP, making sure that the additives determined align with Meta’s overall performance and scalability goals.
Cross-Functional Collaboration
Working along teams all through Meta’s hardware improvement spectrum, you could ensure that the designs are nicely protected into the wider device, contributing to Meta’s contemporary solutions in facts middle infrastructure.
Minimum Qualifications
- To qualify for this characteristic, you want to fulfill the following necessities:
- Bachelor’s Degree in Computer Science, Computer Engineering, or an associated technical hassle.
- At least three years of enjoy in silicon development, with a focus on ASIC format.
- Experience in Verilog or System Verilog for RTL format.
- At least three years of enjoyment in one of the following areas:
- Microstructure and RTL development for complex control and data route IPs.
- SoC micro-architecture layout and integration.
- Power technique improvement or implementation in silicon layout.
Preferred Qualifications
- While not required, the following qualifications will set you apart from other candidates:
- Experience in data path improvement, especially in immoderate-everyday performance, low-latency systems.
- Experience with synthesis and timing closure, making sure that designs meet stringent timing and strength requirements.
- Proven ability to work in a brief-paced, skip-purposeful environment, collaborating with numerous groups to deliver complicated designs under tight closing dates.
Benefits of Working at Meta
Cutting-Edge Innovation
Meta is at the forefront of technological improvements, presenting personnel with the chance to work at the maximum advanced hardware and software responsibilities internationally. As an ASIC Design Engineer, you will be a part of a fixed that pushes the limits of what is viable in silicon format.
Collaborative Work Environment
Meta fosters a collaborative and inclusive subculture in which numerous agencies artwork together to treatment complex traumatic conditions. You should have the possibility to collaborate with specialists in several fields, from hardware engineers to software program developers.
Professional Growth Opportunities
Meta is dedicated to the increase and improvement of its personnel. Whether through mentorship, non-forestall reading, or career development packages, Meta offers a wealth of possibilities to boom professionally.
Comprehensive Benefits Package
Meta offers an aggressive repayment bundle deal that includes complete fitness benefits, retirement plans, and performance-based bonuses. Additionally, personnel revels in generous days without work and well-being applications.
Work on Impactful Projects
At Meta, you can paint on duties that have a real international effect, shaping the destiny of social technology and connectivity. Your artwork will contribute to constructing a greater link internationally, influencing the way people interact for generations to come.
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